For an electron-hole pair to be formed, photon energy $E \ge E_g$. The maximum wavelength corresponds to minimum energy $E = E_g$.
For Si: $\lambda_{max,Si} = 1240 / 1.14 \approx 1087 \text{ nm}$. For Ge: $\lambda_{max,Ge} = 1240 / 0.72 \approx 1722 \text{ nm}$.
Wavelengths between **$1087 \text{ nm}$ and $1722 \text{ nm}$** have enough energy to overcome Ge's gap but not Si's gap.
In an intrinsic semiconductor, $n_e = n_h = n_i$. Total conductivity is $\sigma = n_i e (\mu_e + \mu_h)$.
Since $\mu_e \gg \mu_h$, the electron contribution to conductivity ($n_i e \mu_e$) is much larger than the hole contribution. Therefore, yes, it conducts predominantly via the drift of free **electrons** in the conduction band.
The energy gap depends on the strength of the covalent bonds, which in turn depends on the interatomic distance. Carbon (atomic size small) has very tightly bound valence electrons (strong overlapping), creating a large $E_g$. As we go down the group to Si and Ge, atomic size increases, interatomic spacing increases, and valence electrons are further from the nucleus, resulting in weaker bonds and a **drastically smaller $E_g$**.
Conductivity $\sigma = n_i e (\mu_e + \mu_h)$.
$\sigma = (1.5 \times 10^{16}) \times (1.6 \times 10^{-19}) \times (0.38 + 0.18) = (2.4 \times 10^{-3}) \times 0.56 = 1.344 \times 10^{-3} \ \Omega^{-1}\text{m}^{-1}$.
Resistivity $\rho = 1/\sigma = 1 / (1.344 \times 10^{-3}) \approx \mathbf{744 \ \Omega\cdot\text{m}}$.
(Image Solution - Energy Bands vs Temp)
AI Image Prompt: A clean, mathematically correct landscape diagram comparing the Energy Band structures at Absolute Zero (T=0K) versus Room Temperature (T>0K) for an Intrinsic Semiconductor. Show electrons in the CB and holes in the VB at T>0K, with the Fermi level marked exactly in the middle. The background of the whole image should be fully white.
Filename: Level2_Q5_Intrinsic_Bands_Temperature.png
Ratio $R = \frac{n_i(600)}{n_i(300)} = \frac{e^{-E_g / (2k_B \times 600)}}{e^{-E_g / (2k_B \times 300)}} = e^{\frac{E_g}{2k_B} \left(\frac{1}{300} - \frac{1}{600}\right)} = e^{\frac{E_g}{2k_B} \left(\frac{1}{600}\right)}$.
Exponent $= \frac{1.0}{2 \times 8.62 \times 10^{-5} \times 600} = \frac{1.0}{0.10344} \approx 9.67$.
Ratio $R \approx e^{9.67} \approx \mathbf{1.58 \times 10^4}$. The concentration increases massively.
Extreme hydrostatic pressure compresses the crystal lattice, physically decreasing the interatomic spacing. According to energy band theory (Kronig-Penney model behavior), moving atoms closer together increases the interaction and splitting of atomic orbitals, which typically **widens** the forbidden energy gap ($E_g$) for diamond-like lattices such as Si and Ge.
Energy of $600 \text{ nm}$ photon: $E = \frac{hc}{\lambda} = \frac{1240}{600} \approx 2.07 \text{ eV}$.
Since the incident photon energy ($2.07 \text{ eV}$) is strictly **less than** the bandgap ($2.5 \text{ eV}$), it cannot excite an electron across the gap. Therefore, the photodiode **cannot** detect this signal.
In pure Si, $n_e = n_h = n_i = 1.5 \times 10^{10} \text{ cm}^{-3}$.
Total carrier concentration $n_{total} = n_e + n_h = 2n_i = 3.0 \times 10^{10} \text{ cm}^{-3}$.
For a volume $V = 1 \text{ cm}^3$, total charge carriers = $n_{total} \times V = \mathbf{3.0 \times 10^{10}}$.
In an isolated atom, electrons occupy sharp, discrete energy levels. When $N$ atoms are brought closely together in a crystal, their outer electron wavefunctions overlap. The Pauli Exclusion Principle forbids any two electrons in the entire crystal from having the exact same quantum state. Thus, each degenerate discrete level must split into $N$ closely spaced distinct levels, forming a dense **continuous energy band**.
Drift velocity of electrons $v_e = \mu_e E$ and holes $v_h = \mu_h E$.
Electron current $I_e = n_e e A v_e = n_e e A (\mu_e E)$.
Hole current $I_h = n_h e A v_h = n_h e A (\mu_h E)$.
Dividing the two equations gives: $\mathbf{\frac{I_e}{I_h} = \frac{n_e \mu_e}{n_h \mu_h}}$.
Strictly speaking, **yes, slightly**. While at $0\text{ K}$ it is exactly mid-gap, as temperature rises, the effective mass difference between electrons in the CB and holes in the VB causes the density of available states to differ. To maintain $n_e = n_h$, the Fermi level must shift slightly towards the band with the lower density of states (usually towards the conduction band).
In a semiconductor, rising temperature exponentially generates new charge carriers, overwhelmingly decreasing resistivity (hence, a **negative** coefficient). In a metal, carrier density is fixed; rising temperature only increases random lattice ion vibrations (phonons), which increases electron scattering, thereby increasing resistivity (hence, a **positive** coefficient).
Conductivity $\sigma = n_i e (\mu_e + \mu_h) = (1.5 \times 10^{16})(1.6 \times 10^{-19})(0.135 + 0.048) = 2.4 \times 10^{-3} \times 0.183 = 4.39 \times 10^{-4} \ \Omega^{-1}\text{m}^{-1}$.
Current density $J = \sigma E = (4.39 \times 10^{-4}) \times 100 = \mathbf{4.39 \times 10^{-2} \text{ A/m}^2}$.
Transparency implies the photons do not have enough energy to bridge the bandgap (no absorption).
Energy of $800 \text{ nm}$ photon $E = \frac{1240}{800} = 1.55 \text{ eV}$.
Therefore, the bandgap $E_g$ must be strictly **greater than $1.55 \text{ eV}$** ($E_g > 1.55 \text{ eV}$).
Phosphorus is a pentavalent donor, so $N_D = 5 \times 10^{20} \text{ m}^{-3}$.
Electron concentration $n_e \approx N_D = 5 \times 10^{20} \text{ m}^{-3}$.
Hole concentration $n_h = \frac{n_i^2}{n_e} = \frac{(1.5 \times 10^{16})^2}{5 \times 10^{20}} = \frac{2.25 \times 10^{32}}{5 \times 10^{20}} = \mathbf{4.5 \times 10^{11} \text{ m}^{-3}}$.
Since $n_e \gg n_h$, it is an **n-type** semiconductor.
Ratio $\frac{n_e}{n_h} = \frac{5 \times 10^{20}}{4.5 \times 10^{11}} = \frac{50}{4.5} \times 10^8 = 11.11 \times 10^8 \approx \mathbf{1.11 \times 10^9}$.
(Image Solution - Extrinsic Carrier Conc. Graph)
AI Image Prompt: A clean, mathematically correct landscape graph plotting the natural logarithm of charge carrier concentration (ln n) versus inverse temperature (1/T) for an Extrinsic Semiconductor. Show the three distinct regions: Freeze-out (low T), Extrinsic/Saturation (mid T, flat horizontal line), and Intrinsic (high T, steep slope). The background of the whole image should be fully white.
Filename: Level2_Q18_Extrinsic_Carrier_Temperature.png
Since $N_D > N_A$ ($10^{16} > 5 \times 10^{15}$), the donors overwhelm the acceptors. The semiconductor will be net **n-type**.
The effective donor concentration is $N_D' = N_D - N_A = 10^{16} - 0.5 \times 10^{16} = \mathbf{5 \times 10^{15} \text{ cm}^{-3}}$. This is the approximate majority electron concentration ($n_e$).
In a heavily doped extrinsic semiconductor, there is a massive density of fixed ionized impurity atoms (e.g., $N_D^+$ ions). These fixed ions cause highly frequent **impurity scattering** of the moving charge carriers. This additional collision mechanism reduces the mean free time, thereby slightly lowering the overall mobility compared to a pure intrinsic crystal.
$n_e \approx N_D = 10^{15} \text{ cm}^{-3}$.
Conductivity $\sigma \approx n_e e \mu_e = (10^{15} \text{ cm}^{-3}) \times (1.6 \times 10^{-19} \text{ C}) \times (1350 \text{ cm}^2/\text{Vs})$.
$\sigma = 1.6 \times 1350 \times 10^{-4} = 2160 \times 10^{-4} = \mathbf{0.216 \ \Omega^{-1}\text{cm}^{-1}}$ (or $21.6 \ \Omega^{-1}\text{m}^{-1}$).
The Fermi level indicates the 50% probability state. In an n-type semiconductor, massive doping floods the conduction band with electrons, forcing the 50% probability state (Fermi level) to shift **upwards, closer to the conduction band**. Conversely, in p-type, a massive excess of holes in the valence band pulls the Fermi level **downwards, closer to the valence band**.
Resistivity $\rho = 10 \ \Omega\cdot\text{cm} \implies \sigma = 0.1 \ \Omega^{-1}\text{cm}^{-1}$.
For p-type, $\sigma \approx n_h e \mu_h \approx N_A e \mu_h$.
$N_A = \frac{\sigma}{e \mu_h} = \frac{0.1}{1.6 \times 10^{-19} \times 500} = \frac{0.1}{8 \times 10^{-17}} = \frac{1}{8} \times 10^{16} = \mathbf{1.25 \times 10^{15} \text{ cm}^{-3}}$.
Dopant concentration ($N_D$ or $N_A$) is fixed and does not change with temperature. However, thermal generation of intrinsic carriers ($n_i$) increases exponentially with temperature. At a high enough temperature, the thermally generated $n_i$ becomes vastly larger than the fixed doping concentration. At this point, $n_e \approx n_h \approx n_i$, completely masking the extrinsic properties.
Ionization energy is the tiny energy required to detach the $5^{th}$ valence electron from a donor atom so it becomes a free conduction electron. It is typically very small ($\sim 0.01 - 0.05 \text{ eV}$) because the electron is loosely bound in a high-dielectric medium. It is numerically a small fraction (about 5%) of the large covalent bandgap energy $E_g$ ($\sim 1.1 \text{ eV}$).
Assuming both are heavily doped such that $n_e \approx N_D$ for both, they have the exact same carrier concentration. However, **Germanium (Ge)** inherently has a significantly higher electron mobility ($\sim 3800 \text{ cm}^2/\text{Vs}$) than Silicon ($\sim 1350 \text{ cm}^2/\text{Vs}$). Since $\sigma = n_e e \mu_e$, Sample B (Germanium) will exhibit higher conductivity.
Charge neutrality: $n_e + N_A^- = n_h + N_D^+$. Since it is n-type with no acceptors, $N_A^- = 0$. Assuming all donors are ionized at room temp, $N_D^+ = N_D$.
$n_e = n_h + N_D$. From Mass Action, $n_h = n_i^2/n_e$, giving $n_e = n_i^2/n_e + N_D$.
Since $N_D \gg n_i$, $n_e$ will be large and $n_h$ will be negligible ($n_h \to 0$). Hence, the equation simplifies strictly to $\mathbf{n_e \approx N_D}$.
Boron is a trivalent acceptor. Majority holes $n_h \approx N_A = 10^{17} \text{ cm}^{-3}$.
Minority electrons $n_e = \frac{n_i^2}{n_h} = \frac{(10^{10})^2}{10^{17}} = \frac{10^{20}}{10^{17}} = \mathbf{10^3 \text{ cm}^{-3}}$.
**Yes**. If trivalent acceptors ($N_A$) are added to an existing n-type crystal (having donors $N_D$) such that $N_A > N_D$, the holes generated by the acceptors first recombine with and completely neutralize all the donor electrons. The remaining $(N_A - N_D)$ acceptors then act as the new majority hole source, physically converting the crystal to p-type.
Given $n_h = 10^4 n_e \implies n_e = 10^{-4} n_h$.
Mass Action Law: $n_e n_h = n_i^2 \implies (10^{-4} n_h) n_h = (10^{13})^2$.
$10^{-4} n_h^2 = 10^{26} \implies n_h^2 = 10^{30}$.
Taking square root: $n_h = \mathbf{10^{15} \text{ m}^{-3}}$.
Barrier potential $V_B = E \times d = (5 \times 10^5 \text{ V/m}) \times (1 \times 10^{-6} \text{ m}) = \mathbf{0.5 \text{ V}}$.
This is the defining state of thermal equilibrium. The built-in potential barrier $V_0$ rises just enough to repel the majority of diffusing carriers. The few majority carriers with enough thermal kinetic energy to overcome $V_0$ constitute a small forward diffusion current. This is perfectly counterbalanced by the reverse drift current of thermally generated minority carriers swept down the potential hill. Net current is zero.
(Image Solution - Unbiased Band Diagram)
AI Image Prompt: A clean, mathematically correct landscape diagram showing the Energy Band structure across an unbiased p-n junction. The p-side bands must be shown physically higher than the n-side bands. The Fermi level (Ef) must be a single, straight, continuous horizontal line straight across both regions. The built-in potential barrier (qV0) should be clearly marked as the vertical offset between the conduction bands. The background of the whole image should be fully white.
Filename: Level2_Q33_PN_Junction_Band_Diagram.png
For the junction to remain overall electrically neutral, total uncompensated positive charge must equal total negative charge ($N_A W_p = N_D W_n$). If the p-side is lightly doped ($N_A$ is small), the depletion boundary ($W_p$) must push much further physically into the p-region to uncover an equal number of ions as the heavily doped n-side ($N_D$ is large, $W_n$ is small).
The barrier potential is directly constrained by the intrinsic energy bandgap ($E_g$) of the material. Germanium has a significantly smaller bandgap ($\sim 0.72 \text{ eV}$) than Silicon ($\sim 1.14 \text{ eV}$). A smaller bandgap results in a much larger intrinsic carrier concentration $n_i$, which fundamentally limits the thermodynamic built-in potential $V_0$ that can be established.
Using charge neutrality $N_A x_p = N_D x_n \implies 10^{16} x_p = 10^{15} x_n \implies 10 x_p = x_n$.
Total width $W = x_p + x_n = x_p + 10 x_p = 11 x_p$.
Fraction in p-side $x_p/W = \mathbf{1/11}$. Fraction in n-side $x_n/W = \mathbf{10/11}$.
The "Contact Potential" is another term for the built-in barrier potential $V_0$. **No**, it absolutely cannot drive a steady current through an external resistor. If a circuit is formed, the metal-semiconductor contact potentials at the connecting wires exactly oppose and cancel $V_0$ (thermodynamic equilibrium prevents a perpetual motion energy source).
As temperature increases, thermal generation of electron-hole pairs increases exponentially. This massively increases the minority carrier concentration, which in turn significantly boosts the reverse drift current. To maintain equilibrium ($I_{net}=0$), the opposing forward diffusion current must also increase. This requires the barrier potential $V_0$ to **decrease** (lowering the potential hill).
**No.** The barrier potential creates an opposing electrostatic potential energy hill of height $eV_0 = e(0.7 \text{ V}) = 0.7 \text{ eV}$. Since the electron's kinetic energy ($0.5 \text{ eV}$) is strictly less than the barrier height ($0.7 \text{ eV}$), it does not have enough energy to overcome the field and will be repelled back.
In reverse bias, the fixed uncompensated ions in the depletion layer act exactly as charges on the parallel plates of a capacitor, with the highly insulating depletion region acting as the dielectric. As reverse voltage increases, the depletion layer widens (distance $d$ increases). Since $C = \epsilon A / d$, the junction capacitance **decreases** as reverse voltage increases.
In heavily doped junctions, the depletion layer is incredibly narrow ($< 10^{-6}$ m). Even a small reverse bias voltage ($V$) creates a massive electric field ($E = V/d \approx 10^7 \text{ V/m}$). This intense electric field exerts sufficient electrostatic force to physically rip electrons directly out of their covalent bonds across the junction, causing the sudden massive current known as Zener Breakdown.
$V_0 = \frac{kT}{e} \ln\left( \frac{N_A N_D}{n_i^2} \right) = V_T \ln\left( \frac{N_A N_D}{n_i^2} \right)$.
Change in temperature $\Delta T = 400 - 300 = 100\text{ K}$.
Change in potential $\Delta V_0 = (\text{coefficient}) \times \Delta T = (-2 \text{ mV/K}) \times 100\text{ K} = -200 \text{ mV} = -0.2 \text{ V}$.
New potential $V_0' = 0.75 - 0.2 = \mathbf{0.55 \text{ V}}$.
The positive (Donor) and negative (Acceptor) ions are actual atoms that are rigidly locked into the covalent crystal lattice structure of the semiconductor. Unlike free electrons or holes, they are physically immovable and cannot drift or carry current, regardless of the applied external electric field.
The strong built-in electric field $E$ residing in the depletion region immediately acts on the newly generated electron-hole pair. It violently sweeps the electron towards the n-side and the hole towards the p-side before they have a chance to recombine. This continuous charge separation generates a macroscopic photo-voltage across the terminals.
Diode is forward biased. Voltage across resistor $V_R = 5 - 0.7 = 4.3 \text{ V}$. Current $I = 4.3 / 1000 = 4.3 \text{ mA}$.
Power in resistor $P_R = I^2 R = (4.3 \times 10^{-3})^2 \times 1000 = 18.49 \times 10^{-6} \times 1000 = \mathbf{18.49 \text{ mW}}$.
Power in diode $P_D = V_D \times I = 0.7 \times 4.3 \text{ mA} = \mathbf{3.01 \text{ mW}}$.
(Image Solution - Parallel Diodes Evaluation)
AI Image Prompt: A clean, mathematically correct landscape circuit diagram containing two parallel branches connected to a 10V DC source and a common 2k Ohm series resistor. Branch 1 has Diode D1 (Silicon, forward biased) and Branch 2 has Diode D2 (Silicon, reverse biased). The background of the whole image should be fully white.
Filename: Level2_Q47_Parallel_Diodes_Circuit.png
D1 is forward biased (acts as $0.7\text{V}$ drop). D2 is reverse biased (acts as open circuit, infinite resistance).
Current only flows through D1. The circuit is a series loop with $10\text{V}$, $0.7\text{V}$ drop, and $2\text{k}\Omega$.
$I = \frac{10 - 0.7}{2000} = \frac{9.3}{2000} = 4.65 \times 10^{-3} \text{ A} = \mathbf{4.65 \text{ mA}}$.
Dynamic resistance $r_d = \left( \frac{dI}{dV} \right)^{-1}$.
$\frac{dI}{dV} = I_0 \cdot \left(\frac{e}{kT}\right) e^{eV/kT}$. Since $I \gg I_0$, we approximate $I \approx I_0 e^{eV/kT}$.
So, $\frac{dI}{dV} \approx I \left(\frac{e}{kT}\right)$. Therefore, $r_d = \mathbf{\frac{kT}{eI}}$. (At room temp, $kT/e \approx 26 \text{ mV}$, so $r_d \approx 26\text{mV} / I$).
Ripple factor $\gamma = \sqrt{(I_{rms}/I_{DC})^2 - 1}$.
For HWR: $\gamma \approx \mathbf{1.21}$ (or $121\%$). For FWR: $\gamma \approx \mathbf{0.48}$ (or $48\%$).
FWR is vastly superior because its ripple factor is less than half that of HWR, meaning its output is physically much closer to a pure steady DC line, making it much easier and cheaper to smooth out with capacitor filters.
Secondary total $V_{rms} = 220 / 10 = 22 \text{ V}$. Secondary total peak $V_{m,total} = 22\sqrt{2} \approx 31.11 \text{ V}$.
For a center-tapped transformer, half the voltage is applied across the load: $V_m = 31.11 / 2 = \mathbf{15.55 \text{ V}}$ (Peak DC Output).
PIV required for diodes in Center-Tapped FWR is $2 V_m = 2 \times 15.55 = \mathbf{31.11 \text{ V}}$.
(Image Solution - Bridge Rectifier)
AI Image Prompt: A clean, mathematically correct landscape circuit diagram of a Bridge Rectifier using 4 diodes (D1, D2, D3, D4) connected to an AC source. Show the load resistor Rl across the bridge. Draw arrows showing the path of current during the positive half-cycle. The background of the whole image should be fully white.
Filename: Level2_Q51_Bridge_Rectifier_Circuit.png
1. **Transformer Utilization:** A bridge rectifier utilizes the full secondary winding continuously throughout the cycle (higher Transformer Utilization Factor), eliminating the need for a bulky, expensive center-tapped transformer.
2. **PIV:** The diodes in a bridge rectifier only need to withstand a PIV of $V_m$, whereas diodes in a center-tapped setup must withstand a PIV of $2V_m$.
With no load, all current flows through the Zener diode. Voltage drop across $R_S$ is $V_R = V_{in} - V_Z$.
$I_{min} = \frac{V_{in(min)} - V_Z}{R_S} = \frac{10 - 6}{100} = \frac{4}{100} = \mathbf{40 \text{ mA}}$.
$I_{max} = \frac{V_{in(max)} - V_Z}{R_S} = \frac{15 - 6}{100} = \frac{9}{100} = \mathbf{90 \text{ mA}}$.
**Zener Breakdown** occurs in *heavily doped* diodes (thin depletion layer). The massive electric field directly rips valence electrons out of covalent bonds.
**Avalanche Breakdown** occurs in *lightly doped* diodes (wide depletion layer). Thermally generated minority carriers are accelerated to high kinetic energies and collide with atoms, knocking out secondary electrons in a multiplying chain reaction (avalanche).
Peak input voltage $V_m = 200 \text{ V}$. Total resistance $R = R_L + R_f = 2000 + 10 = 2010 \ \Omega$.
Peak current $I_m = \frac{V_m}{R} = \frac{200}{2010} \approx 0.0995 \text{ A}$.
For a Half-Wave Rectifier, average DC current $I_{DC} = \frac{I_m}{\pi} = \frac{0.0995}{3.1415} \approx \mathbf{0.0316 \text{ A}}$ (or $31.6 \text{ mA}$).
Reverse saturation current ($I_0$) is strictly dictated by the number density of thermally generated minority charge carriers ($n_i^2$). Based on the thermodynamic Boltzmann factor ($n_i^2 \propto e^{-E_g/kT}$), calculating the exponential derivative shows that for semiconductor bandgaps like Ge ($0.72 \text{ eV}$), a $10\text{K}$ (or $10^\circ\text{C}$) rise in absolute temperature mathematically doubles the intrinsic generation rate, hence doubling $I_0$.
The capacitor discharges during time interval $T \approx 1/2f$ (for full wave, frequency is $2f$).
Charge lost $\Delta Q \approx I_{DC} \times T = I_{DC} \times \frac{1}{2f}$.
Since $\Delta Q = C \Delta V$, we get $C \Delta V = \frac{I_{DC}}{2f}$.
Therefore, ripple voltage $\mathbf{\Delta V = \frac{I_{DC}}{2 f C}}$.
**LED:** Operates in **Forward Bias**. It converts electrical energy into light energy (injected majority carriers recombine radiatively at the junction, emitting photons).
**Photodiode:** Operates in **Reverse Bias**. It converts light energy into electrical energy (incident photons break bonds in the depletion layer, creating electron-hole pairs that are swept by the field, generating photocurrent).
Efficiency $\eta = \frac{P_{DC}}{P_{AC\_in}} \times 100\%$.
$P_{DC} = I_{DC}^2 R_L = (\frac{2I_m}{\pi})^2 R_L = \frac{4 I_m^2}{\pi^2} R_L$.
$P_{AC} = I_{rms}^2 R_L = (\frac{I_m}{\sqrt{2}})^2 R_L = \frac{I_m^2}{2} R_L$.
$\eta = \frac{4/\pi^2}{1/2} \times 100\% = \frac{8}{\pi^2} \times 100\% \approx \mathbf{81.2\%}$.
A heavily doped Zener diode undergoes Zener breakdown based on pure electric field emission (tunneling). If the temperature is decreased, the crystal lattice contracts slightly and bandgap effectively widens. This makes tunneling mechanically harder, meaning a **higher** electric field (and thus higher voltage) is required. Therefore, Zener breakdown voltage has a **negative temperature coefficient** (decreases with heating, increases with cooling).
Expression: $Y = A\overline{B} + \overline{A}B$
Truth Table:
| A | B | Y |
|---|---|---|
| 0 | 0 | 0 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 0 |
Circuit: Pass A and B through NOT gates to get $\overline{A}, \overline{B}$. Feed $(A,\overline{B})$ into an AND gate. Feed $(\overline{A},B)$ into a second AND gate. Connect the outputs of both AND gates into a final OR gate.
$Y = A\overline{B}C + A\overline{B}\overline{C} + \overline{A}\overline{B}C + \overline{A}\overline{B}\overline{C}$
Group terms: $Y = A\overline{B}(C + \overline{C}) + \overline{A}\overline{B}(C + \overline{C})$.
Since $C + \overline{C} = 1$: $Y = A\overline{B} + \overline{A}\overline{B}$.
Factor $\overline{B}$: $Y = \overline{B}(A + \overline{A})$.
Since $A + \overline{A} = 1$: $Y = \mathbf{\overline{B}}$.
(Image Solution - 3-Input Logic Evaluation)
AI Image Prompt: A clean, mathematically correct landscape circuit diagram of a logic gate network. Input A and Input B go into a NAND gate. The output of this NAND gate and Input C go into an OR gate. The final output is Y. The background of the whole image should be fully white.
Filename: Level2_Q63_3Input_Logic_Circuit.png
NAND output is $\overline{A \cdot B}$. OR gate takes this and C.
Expression: $Y = \overline{A \cdot B} + C$.
Evaluate for $A=1, B=1, C=0$: $Y = \overline{1 \cdot 1} + 0 = \overline{1} + 0 = 0 + 0 = \mathbf{0}$.
Inputs A and B pass through NOT gates, becoming $\overline{A}$ and $\overline{B}$.
These enter a NOR gate, whose fundamental logic is $\overline{(\text{Input}_1 + \text{Input}_2)}$.
$Y = \overline{\overline{A} + \overline{B}}$.
Applying De Morgan's Law ($\overline{X + Y} = \overline{X} \cdot \overline{Y}$):
$Y = \overline{\overline{A}} \cdot \overline{\overline{B}} = \mathbf{A \cdot B}$. This is the exact definition of an AND gate.
Truth Table:
| A | B | Sum | Carry |
| 0 | 0 | 0 | 0 |
| 0 | 1 | 1 | 0 |
| 1 | 0 | 1 | 0 |
| 1 | 1 | 0 | 1 |
Logic analysis: Sum is 1 when inputs differ $\implies$ **XOR gate** ($Sum = A \oplus B$). Carry is 1 only when both are 1 $\implies$ **AND gate** ($Carry = A \cdot B$).
Three NAND gates needed. Tie inputs of Gate 1 together for signal A $\implies$ output is $\overline{A}$. Tie inputs of Gate 2 together for signal B $\implies$ output is $\overline{B}$. Feed these two outputs into Gate 3.
$Y = \overline{\overline{A} \cdot \overline{B}}$.
By De Morgan's Law: $Y = \overline{\overline{A}} + \overline{\overline{B}} = \mathbf{A + B}$ (Standard OR gate).
Inputs to AND gate: A, B. Output = $AB$.
Inputs to EX-OR gate: $AB$ and $1$. Logic of EX-OR is $X \oplus Y = X\overline{Y} + \overline{X}Y$.
Here $X = AB$ and $Y = 1$. $\implies Y_{out} = (AB)\overline{1} + \overline{(AB)}(1)$.
$Y_{out} = (AB)(0) + \overline{AB}(1) = \mathbf{\overline{AB}}$. This is exactly a **NAND gate**.
(Image Solution - Timing Diagram Evaluation)
AI Image Prompt: A clean, mathematically correct landscape timing diagram showing waveforms for Inputs A, B and Output Y. A: 0, 0, 1, 1. B: 0, 1, 0, 1. Y: 1, 0, 0, 1. (This corresponds to an XNOR gate). The background of the whole image should be fully white.
Filename: Level2_Q68_Timing_Diagram_XNOR.png
Reading the graph pulse by pulse:
(A=0, B=0) $\to Y=1$
(A=0, B=1) $\to Y=0$
(A=1, B=0) $\to Y=0$
(A=1, B=1) $\to Y=1$
Output is 1 when inputs are equal. This is the **Exclusive-NOR (XNOR)** gate.
Use distributive law on the last two brackets: $(\overline{A} + C)(B + C) = \overline{A}B + \overline{A}C + CB + CC$. Since $CC = C$ and $C(1 + \overline{A} + B) = C$, this reduces to $\overline{A}B + C$.
Now multiply by first bracket: $Y = (A + B)(\overline{A}B + C) = A\overline{A}B + AC + B\overline{A}B + BC$.
$A\overline{A} = 0$, $BB = B$. So $Y = AC + \overline{A}B + BC$. By consensus theorem (or expanding $BC = BC(A+\overline{A})$), the $BC$ term is redundant. $Y = \mathbf{AC + \overline{A}B}$.
A Universal Gate (NAND or NOR) is one that can implement any Boolean logic operation without requiring any other type of gate. To make a NOR gate act as a NOT gate, physically tie its two inputs together so they share the exact same signal $A$.
Output $Y = \overline{A + A}$. Since $A + A = A$ in Boolean algebra, $Y = \mathbf{\overline{A}}$.
Create a minterm for each condition where output is 1.
For (0,1,0): $\overline{A}B\overline{C}$
For (1,0,1): $A\overline{B}C$
For (1,1,1): $ABC$
SOP Expression: $Y = \mathbf{\overline{A}B\overline{C} + A\overline{B}C + ABC}$.
Apply De Morgan's Law to break the top bar: $\overline{X + Y} = \overline{X} \cdot \overline{Y}$.
Let $X = \overline{A}$ and $Y = \overline{B}$.
$Y = \overline{\overline{A}} \cdot \overline{\overline{B}} = \mathbf{A \cdot B}$.
This expression corresponds to an **AND gate**.
A physical AND gate operates on voltages: Output is High only if A is High AND B is High.
In negative logic, High voltage = Logic 0, Low voltage = Logic 1. The electrical rule becomes: Output is 0 only if A is 0 AND B is 0. In all other cases (where at least one is Low voltage/Logic 1), the output is Low voltage/Logic 1.
This truth table (0,0 $\to$ 0; else 1) is the exact mathematical definition of an **OR gate**.
XOR logic is $Y = A\overline{B} + \overline{A}B$. Substitute $B$ with $A$.
$Y = A\overline{A} + \overline{A}A = 0 + 0 = \mathbf{0}$.
**No.** The output is permanently zero (grounded) regardless of whether input $A$ is 1 or 0.
Majority means 2 or 3 inputs are 1. The combinations giving Y=1 are: (0,1,1), (1,0,1), (1,1,0), and (1,1,1).
SOP: $Y = \overline{A}BC + A\overline{B}C + AB\overline{C} + ABC$.
Add $ABC$ twice (since $X+X=X$): $Y = (\overline{A}BC + ABC) + (A\overline{B}C + ABC) + (AB\overline{C} + ABC)$.
$Y = BC(\overline{A}+A) + AC(\overline{B}+B) + AB(\overline{C}+C) = \mathbf{BC + AC + AB}$.
