Vardaan Institute - Physics Solutions Key (Level 1)

Topic 14.1: Energy Bands: Classification of Solids

1.Answer:

The energy gap ($E_g$) between the valence band and conduction band is much larger for Carbon (diamond) ($\approx 5.4 \text{ eV}$) making it an insulator. For Silicon ($1.1 \text{ eV}$) and Germanium ($0.7 \text{ eV}$), $E_g$ is small enough for thermal energy at room temperature to excite electrons into the conduction band, making them semiconductors.

2.Answer:

Energy of photon $E = \frac{hc}{\lambda}$. For electron-hole pair generation, $E \ge E_g$.
Maximum wavelength $\lambda_{max}$ corresponds to minimum energy $E_g$.
$\lambda_{max} = \frac{hc}{E_g} = \frac{1240 \text{ eV}\cdot\text{nm}}{1.1 \text{ eV}} \approx \mathbf{1127 \text{ nm}}$. (Infrared region).

3.Answer:

The Fermi energy level is the highest energy level occupied by an electron at $0\text{ K}$. In an intrinsic semiconductor at $T > 0\text{ K}$, it is the energy level where the probability of finding an electron is exactly $50\%$. It lies almost exactly in the middle of the forbidden energy gap.

4.Answer:

(Image Solution - Resistivity vs Temp Graph)

AI Image Prompt: A clean, high-quality, mathematically correct landscape graph showing the variation of electrical resistivity (rho) with absolute temperature (T) for a typical semiconductor. The curve should clearly show an exponential decay. Label the axes as Resistivity (y-axis) and Temperature (x-axis). The background of the whole image should be fully white.

Filename: Level1_Q4_Resistivity_Temperature_Graph.png

5.Answer:

As temperature rises, more covalent bonds break due to thermal energy. The number density of charge carriers ($n_e, n_h$) increases exponentially ($n_i \propto e^{-E_g / 2kT}$). This exponential increase in charge carriers completely dominates the slight decrease in mobility, causing conductivity to rise exponentially. In metals, carrier concentration is constant, but lattice vibrations increase, lowering conductivity.

6.Answer:

Because the energy gap is greater than $3 \text{ eV}$ (it is $6.5 \text{ eV}$), thermal energy at room temperature is highly insufficient to excite electrons to the conduction band. Therefore, it is a perfect **Insulator**.

7.Answer:

The forbidden energy gap ($E_g$) represents a region of energy states that electrons are quantum-mechanically not allowed to occupy. Physically, it signifies the minimum energy an electron bound in a covalent bond (valence band) must acquire to break free and become a mobile charge carrier (conduction band).

8.Answer:

The material is **opaque**. Visible light photons have energies between $1.8 \text{ eV}$ and $3.1 \text{ eV}$. Since these photon energies are greater than the bandgap ($0.7 \text{ eV}$), the electrons in the valence band will readily absorb the light to jump to the conduction band. Absorbed light means the material is opaque.

9.Answer:

Total conductivity $\sigma = \sigma_e + \sigma_h = e n_e \mu_e + e n_h \mu_h$.
For an intrinsic semiconductor, $n_e = n_h = n_i$.
Therefore, $\sigma = \mathbf{n_i e (\mu_e + \mu_h)}$.

10.Answer:

$\sigma = n_i e (\mu_e + \mu_h) = (1.5 \times 10^{16}) \times (1.6 \times 10^{-19}) \times (0.14 + 0.05)$
$\sigma = (2.4 \times 10^{-3}) \times (0.19) = \mathbf{4.56 \times 10^{-4} \text{ S}\cdot\text{m}^{-1}}$ (or $\Omega^{-1}\text{m}^{-1}$).

11.Answer:

Electrons move freely through the relatively empty conduction band. Holes, however, represent empty states in the almost-filled valence band. Hole motion actually requires neighboring bound valence electrons to break and jump into the empty state, which is a more restricted, slower process. Hence, $\mu_e > \mu_h$.

12.Answer:

A 'valence electron' occupies energy states in the **Valence Band** and is bound to the parent atom (participating in covalent bonds). A 'free electron' has acquired enough energy to jump across the forbidden gap into the **Conduction Band**, where it is free to move through the crystal lattice under an electric field.

13.Answer:

When an electron falls from the higher-energy conduction band to recombine with a hole in the lower-energy valence band, the energy difference (which is $\ge E_g$) is released. This energy is emitted either as a photon (light, as in LEDs) or as a phonon (heat/lattice vibration).

14.Answer:

The width of the forbidden energy gap ($E_g$) **decreases slightly** as the temperature increases. This is due to the thermal expansion of the crystal lattice and changing interatomic spacing, which alters the potential energy experienced by the electrons.

15.Answer:

Elemental: **Silicon (Si)** and **Germanium (Ge)**.
Compound: **Gallium Arsenide (GaAs)** and **Cadmium Sulfide (CdS)** (or Indium Phosphide InP).

Topic 14.2: Types of Semiconductors (Intrinsic/Extrinsic)

16.Answer:

1 ppm (part per million) means 1 Sb atom per $10^6$ Si atoms.
Number density of Sb atoms $N_D = \frac{5 \times 10^{28}}{10^6} = 5 \times 10^{22} \text{ m}^{-3}$.
Since each Sb (pentavalent) donates 1 electron, $n_e \approx N_D = \mathbf{5 \times 10^{22} \text{ m}^{-3}}$.

17.Answer:

Using the Mass Action Law: $n_e \cdot n_h = n_i^2$.
$n_h = \frac{n_i^2}{n_e} = \frac{(1.5 \times 10^{16})^2}{5 \times 10^{22}} = \frac{2.25 \times 10^{32}}{5 \times 10^{22}} = \mathbf{4.5 \times 10^9 \text{ m}^{-3}}$.
(Notice $n_h \ll n_e$, verifying it is an n-type semiconductor).

18.Answer:

(Image Solution - Extrinsic Energy Bands)

AI Image Prompt: A clean, high-quality, mathematically correct landscape diagram comparing the Energy Band diagrams of an n-type and a p-type semiconductor side by side. For the n-type, clearly show the Donor energy level (Ed) just below the Conduction Band (CB). For the p-type, clearly show the Acceptor energy level (Ea) just above the Valence Band (VB). Label majority and minority carriers. The background of the whole image should be fully white.

Filename: Level1_Q18_Extrinsic_Energy_Bands.png

19.Answer:

Trivalent impurities have 3 valence electrons. When they replace Si (4 valence electrons), one covalent bond is left incomplete, creating a vacancy or 'hole'. Since this impurity 'accepts' an electron from the lattice to complete the bond, creating a mobile positive hole, it results in a 'p-type' (positive-type) semiconductor where holes are majority carriers.

20.Answer:

Energy required to free the donor electron is $E = 0.05 \text{ eV}$.
$\lambda_{max} = \frac{hc}{E} = \frac{1240 \text{ eV}\cdot\text{nm}}{0.05 \text{ eV}} = \mathbf{24800 \text{ nm}}$ (or $24.8 \text{ \mu m}$).

21.Answer:

$n_e = 8 \times 10^{13} \text{ cm}^{-3}$ and $n_h = 5 \times 10^{12} \text{ cm}^{-3}$.
Since $n_e > n_h$ (electrons outnumber holes), the semiconductor is strictly **n-type**.

22.Answer:

From Mass Action Law: $n_i^2 = n_e \cdot n_h$.
$n_i = \sqrt{n_e \cdot n_h} = \sqrt{(8 \times 10^{13}) \times (5 \times 10^{12})} = \sqrt{40 \times 10^{25}} = \sqrt{4 \times 10^{26}}$.
$n_i = \mathbf{2 \times 10^{13} \text{ cm}^{-3}}$.

23.Answer:

**Yes, for an intrinsic semiconductor**. Thermal generation breaks covalent bonds, always producing an electron-hole pair simultaneously. Therefore, the ratio $n_e/n_h$ remains strictly $1:1$ regardless of temperature. (For an extrinsic semiconductor, the ratio approaches 1 at very high temperatures).

24.Answer:

Extrinsic semiconductors are formed by replacing neutral host atoms with neutral impurity atoms. The extra mobile electron (in n-type) or mobile hole (in p-type) is perfectly balanced by an immovable, positively charged donor ion or negatively charged acceptor ion fixed in the lattice. Therefore, the net macroscopic charge is exactly zero.

25.Answer:

Intrinsic semiconductors rely purely on thermal energy to break bonds for conduction ($n_i$ depends heavily on $T$). Extrinsic semiconductors owe their high conductivity primarily to doping; their majority carrier concentration ($n_e \approx N_D$ or $n_h \approx N_A$) is virtually independent of normal temperature variations, making them practically stable for devices.

26.Answer:

If both donors and acceptors are present, they compensate each other. Since $N_D \gg N_A$, it is an n-type semiconductor. The majority carrier concentration (electrons) is roughly equal to the net effective donor concentration: $\mathbf{n_e \approx N_D - N_A}$.

27.Answer:

Arsenic is a pentavalent (donor) impurity. It introduces a new, discrete allowed energy level called the **Donor Energy Level ($E_d$)** situated in the forbidden gap, just slightly below the bottom of the conduction band.

28.Answer:

The $5^{th}$ valence electron of a donor atom is not part of any covalent bond. It is only loosely bound to its parent ion by a weak electrostatic Coulomb force (which is further shielded by the high dielectric constant of the semiconductor). Thus, very little energy ($~0.05 \text{ eV}$) is needed to detach it compared to breaking a strong covalent bond ($E_g \sim 1.1 \text{ eV}$).

29.Answer:

**No.** Carbon is a tetravalent element (Group 14), exactly like Silicon. Replacing a Silicon atom with a Carbon atom will simply form four regular covalent bonds without creating any extra free electrons or holes. Therefore, no extrinsic charge carriers are generated.

30.Answer:

At very high temperatures, immense thermal energy breaks massive numbers of host covalent bonds, generating a huge intrinsic concentration ($n_i$) of electron-hole pairs. This thermally generated $n_i$ completely overwhelms the fixed impurity concentration ($N_D$ or $N_A$), making $n_e \approx n_h \approx n_i$, so the extrinsic nature is lost.

Topic 14.3: p-n Junction Formation & Barrier Potential

31.Answer:

1. **Diffusion:** Due to concentration gradients, majority holes from p-side diffuse to n-side, and majority electrons from n-side diffuse to p-side.
2. **Drift:** The uncompensated ions left behind create an internal electric field. This field sweeps minority carriers across the junction (holes from n to p, electrons from p to n), opposing the diffusion.

32.Answer:

$E = \frac{V_B}{d} = \frac{0.6 \text{ V}}{5 \times 10^{-7} \text{ m}} = 0.12 \times 10^7 = \mathbf{1.2 \times 10^6 \text{ V/m}}$.

33.Answer:

If doping concentration is heavily increased, the required amount of fixed space charge to establish the necessary barrier potential is achieved in a very short physical distance. Therefore, the width of the depletion layer **decreases (becomes narrower)**.

34.Answer:

(Image Solution - PN Junction Graphs)

AI Image Prompt: A clean, high-quality, mathematically correct landscape graph showing the variation of charge density (rho) and electrical potential (V) across an unbiased p-n junction. The x-axis should represent distance across the junction (from p-side to n-side). The charge density should show a negative rectangular pulse on the p-side and a positive pulse on the n-side. The potential graph should show a smooth step function indicating the barrier potential (V0). The background of the whole image should be fully white.

Filename: Level1_Q34_PN_Junction_Potential_Graph.png

35.Answer:

Higher temperatures generate significantly more minority carriers on both sides due to increased thermal bond breaking. These increased minority carriers are swept across by the built-in field (drift current), partially neutralizing the space charge layer ions, which inherently **decreases** the barrier potential.

36.Answer:

As holes diffuse to the n-side, they leave behind fixed negative acceptor ions. As electrons diffuse to the p-side, they leave fixed positive donor ions. This creates a strong internal electric field pointing from n to p. This field exerts an opposing force that rapidly halts further diffusion of majority carriers.

37.Answer:

Drift current is the motion of charge carriers swept across the depletion region by the built-in electric field. It is constituted entirely by the thermally generated **Minority Charge Carriers** (electrons from p-side to n-side, and holes from n-side to p-side).

38.Answer:

They are called fixed or immobile **ions**. On the p-side, there are negative Acceptor ions. On the n-side, there are positive Donor ions.

39.Answer:

$E = \frac{V_B}{d} \implies d = \frac{V_B}{E}$.
$d = \frac{0.7}{2 \times 10^6} = 0.35 \times 10^{-6} \text{ m} = \mathbf{0.35 \text{ \mu m}}$.

40.Answer:

It is called the "depletion region" because it is physically completely **depleted of mobile majority charge carriers**. All mobile electrons and holes that were in this narrow zone have diffused away and recombined, leaving only rigid lattice ions.

41.Answer:

**Yes**. The barrier potential is an intrinsic property of the bandgap of the semiconductor material. Typical values at room temperature are $\approx 0.7 \text{ V}$ for Silicon and $\approx 0.3 \text{ V}$ for Germanium.

42.Answer:

**No.** The metal contacts of the voltmeter probes form metal-semiconductor junctions at the diode terminals. These contact potentials perfectly and exactly cancel the internal barrier potential in a closed loop, resulting in a zero reading on the voltmeter.

43.Answer:

To maintain overall charge neutrality, the total positive space charge must equal the total negative space charge. Since the p-side is lightly doped (fewer ions per unit volume), the depletion region must penetrate **more deeply into the p-side** to uncover enough ions.

44.Answer:

Equilibrium is established when the built-in barrier potential becomes exactly strong enough so that the forward **Diffusion Current** of majority carriers is perfectly balanced and canceled out by the reverse **Drift Current** of minority carriers ($I_{diffusion} = I_{drift}$).

45.Answer:

The depletion layer acts as a dielectric insulator because it lacks mobile charges. The neutral p and n regions bounding it act as conducting plates. This physically forms a parallel-plate capacitor structure, inherently giving the p-n junction a measurable capacitance.

Topic 14.4: Diode Applications (Biasing & Rectifiers)

46.Answer:

(Image Solution - Identifying Biasing)

AI Image Prompt: A clean, high-quality, mathematically correct landscape circuit diagram containing three independent simple circuits labeled (a), (b), and (c). Each circuit contains a single p-n junction diode and a resistor connected to a battery. Circuit (a): p-side to +5V, n-side to Ground through resistor. Circuit (b): p-side to Ground, n-side to +5V through resistor. Circuit (c): p-side to -2V, n-side to -5V through resistor. The background of the whole image should be fully white.

Filename: Level1_Q46_Diode_Biasing_Identify.png

(a) **Forward Biased** (p is higher potential than n: $5\text{V} > 0\text{V}$).
(b) **Reverse Biased** (n is higher potential than p: $5\text{V} > 0\text{V}$).
(c) **Forward Biased** (p is higher potential than n: $-2\text{V} > -5\text{V}$).

47.Answer:

In Forward Bias, the applied external voltage opposes the built-in internal electric field. This pushes majority carriers towards the junction, neutralizing some fixed ions. As a result, the width of the depletion layer **decreases**, and the effective potential barrier is severely **lowered**, allowing heavy current flow.

48.Answer:

An ideal diode in forward bias acts as a short circuit (0 V drop).
Using Ohm's law: $I = \frac{V}{R} = \frac{5}{100} = \mathbf{0.05 \text{ A}}$ (or 50 mA).

49.Answer:

For a practical Silicon diode, there is a voltage drop of $0.7 \text{ V}$ across it.
Net voltage available for resistor $V_{net} = 5 - 0.7 = 4.3 \text{ V}$.
Current $I = \frac{V_{net}}{R} = \frac{4.3}{100} = \mathbf{0.043 \text{ A}}$ (or 43 mA).

50.Answer:

It is the tiny leakage current flowing in reverse bias strictly due to the drift of thermally generated minority carriers. It is independent of applied voltage because the strong reverse field easily sweeps all available minority carriers across. Its magnitude is entirely limited by the rate of thermal generation, not the voltage.

51.Answer:

Because the V-I curve is non-linear, a diode does not obey Ohm's law statically. Dynamic resistance ($r_d$) is the ratio of a small change in voltage to the resulting small change in current in the linear active region. $r_d = \frac{\Delta V}{\Delta I}$.

52.Answer:

In a half-wave rectifier, there is exactly one positive pulse output for every full input AC cycle. Therefore, the ripple frequency is equal to the input frequency: $\mathbf{f_{ripple} = 50 \text{ Hz}}$.

53.Answer:

In a full-wave rectifier, both the positive and negative half-cycles of the input are inverted to produce two output pulses per single input cycle. Hence, the ripple frequency is twice the input frequency: $f_{ripple} = 2 \times 60 = \mathbf{120 \text{ Hz}}$.

54.Answer:

(Image Solution - Filter Circuit)

AI Image Prompt: A clean, high-quality, mathematically correct landscape diagram showing the complete circuit of a Half-Wave Rectifier with a step-down transformer, a single diode, a load resistor (RL), and a parallel capacitor filter (C). Show the input sine wave and the smoothed output DC waveform. The background of the whole image should be fully white.

Filename: Level1_Q54_Half_Wave_Rectifier_Filter.png

The parallel capacitor charges up to the peak voltage during the conduction half-cycle. During the non-conduction half-cycle when the diode is reverse biased, the capacitor discharges slowly through the load resistor ($R_L$). This sustained discharge supplies current to the load, significantly filling in the gaps and smoothing the pulsating DC ripples into a steadier DC voltage.

55.Answer:

Peak Inverse Voltage (PIV) is the maximum reverse voltage a diode must safely withstand without suffering breakdown during its non-conducting half-cycle. In a center-tapped full-wave rectifier, the non-conducting diode experiences the full voltage of the entire secondary winding. Thus, required $\mathbf{PIV \ge 2V_m}$.

56.Answer:

At the breakdown voltage, a massive number of covalent bonds are shattered, flooding the depletion region with free charge carriers. This occurs due to either **Zener Breakdown** (strong electric field directly ripping electrons from bonds) or **Avalanche Breakdown** (high-speed minority carriers colliding and knocking out secondary electrons).

57.Answer:

Forward current $I_f = \frac{V}{R_f} = \frac{2}{25} = 0.08 \text{ A}$.
Reverse current $I_r = \frac{V}{R_r} = \frac{2}{10^6} = 2 \times 10^{-6} \text{ A}$.
Ratio $I_f / I_r = \frac{0.08}{2 \times 10^{-6}} = 0.04 \times 10^6 = \mathbf{40,000 : 1}$.

58.Answer:

If the center tap is disconnected, the return path for the current through the load is broken. Neither diode can complete a circuit back to the transformer. The output voltage across the load will drop to **strictly zero**.

59.Answer:

1. It utilizes both halves of the AC input cycle, resulting in significantly **higher efficiency** and higher average DC output voltage.
2. The ripple frequency is doubled, making the output **much easier to filter** and smooth using smaller capacitors.

60.Answer:

**No.** A transformer operates purely on the principle of electromagnetic induction (Faraday's Law), which absolutely requires a *changing* magnetic flux. A steady DC current produces a constant, unchanging magnetic field, inducing zero EMF in the secondary coil.

Topic 14.5: Logic Gates (Mains Focus)

61.Answer:

NOR gate is OR followed by NOT ($Y = \overline{A+B}$).
| A | B | A+B | Y (NOR) |
|---|---|-----|---------|
| 0 | 0 | 0 | **1** |
| 0 | 1 | 1 | **0** |
| 1 | 0 | 1 | **0** |
| 1 | 1 | 1 | **0** |

62.Answer:

For A=1, B=1: $Y = 1\cdot\overline{1} + \overline{1}\cdot1 = 1\cdot0 + 0\cdot1 = 0 + 0 = \mathbf{0}$.
For A=0, B=1: $Y = 0\cdot\overline{1} + \overline{0}\cdot1 = 0\cdot0 + 1\cdot1 = 0 + 1 = \mathbf{1}$.
This expression specifically represents the **Exclusive-OR (XOR)** gate.

63.Answer:

(Image Solution - Logic Circuit Evaluation)

AI Image Prompt: A clean, high-quality, mathematically correct landscape circuit diagram showing a logic gate network. Two inputs A and B go into an OR gate. The output of the OR gate goes into one input of an AND gate. The second input of the AND gate is connected to input A through a NOT gate. Label the final output Y. The background of the whole image should be fully white.

Filename: Level1_Q63_Logic_Circuit_Evaluation.png

Output of the OR gate is $(A + B)$.
Output of the NOT gate is $\overline{A}$.
These two feed into the AND gate. Final output $Y = \mathbf{(A + B) \cdot \overline{A}}$.
*(Note: This simplifies to $A\overline{A} + B\overline{A} = 0 + \overline{A}B = \overline{A}B$).*

64.Answer:

First Theorem (NOR logic): $\overline{A + B} = \overline{A} \cdot \overline{B}$
Second Theorem (NAND logic): $\overline{A \cdot B} = \overline{A} + \overline{B}$

65.Answer:

**Three** NAND gates are required.
1. Use gate 1 to invert A: $Y_1 = \overline{A \cdot A} = \overline{A}$.
2. Use gate 2 to invert B: $Y_2 = \overline{B \cdot B} = \overline{B}$.
3. Feed $Y_1$ and $Y_2$ into gate 3: $Y = \overline{Y_1 \cdot Y_2} = \overline{\overline{A} \cdot \overline{B}}$.
By De Morgan's Law, $Y = A + B$ (which is an OR gate).

66.Answer:

An AND gate gives $1$ only when both inputs are $1$. If the output is $0$ exclusively under this exact condition, it must be the exact inverse of an AND gate. Therefore, it is a **NAND gate**.

67.Answer:

Factor out A: $Y = A(1 + B)$.
In Boolean algebra, anything ORed with 1 is always 1 ($1 + B = 1$).
Therefore, $Y = A(1) = \mathbf{A}$.

68.Answer:

(Image Solution - Timing Diagram Evaluation)

AI Image Prompt: A clean, high-quality, mathematically correct landscape diagram showing three timing waveforms (voltage vs time graphs) labeled A, B, and Y. Waveforms A and B are the inputs. Waveform Y is the output. A shows pulses: low, high, low, high. B shows: low, low, high, high. Y shows: high, low, low, low. The background of the whole image should be fully white.

Filename: Level1_Q68_Timing_Diagram_Identify.png

Reading the graph pulse by pulse:
(0,0) -> Y=1; (1,0) -> Y=0; (0,1) -> Y=0; (1,1) -> Y=0.
This is the exact truth table of a **NOR gate**.

69.Answer:

An AND gate followed by a NOT gate is logically equivalent to a **NAND gate**. Its symbol is the standard D-shaped AND symbol with a small inversion bubble at the output tip.

70.Answer:

Output of NOR is $Y = \overline{A + B}$. If inputs are shorted, $B = A$.
$Y = \overline{A + A}$. In Boolean algebra, $A + A = A$.
Therefore, $Y = \mathbf{\overline{A}}$. It behaves exactly as a **NOT gate** (Inverter).

71.Answer:

$Y = A \oplus B = \mathbf{A\overline{B} + \overline{A}B}$.

72.Answer:

1. Connect inputs A and B to an AND gate (output is $A \cdot B$).
2. Pass this output through a NOT gate (output is $\overline{A \cdot B}$).
3. Connect this inverted output and input C to a 2-input OR gate. The final output is $Y = \overline{A \cdot B} + C$.

73.Answer:

Expand the expression: $Y = A\cdot A + A\cdot\overline{B} + B\cdot A + B\cdot\overline{B}$.
Since $A\cdot A = A$ and $B\cdot\overline{B} = 0$, $Y = A + A\overline{B} + AB$.
Factor A: $Y = A(1 + \overline{B} + B) = A(1 + 1) = A(1) = \mathbf{A}$.

74.Answer:

An AND gate outputs 1 strictly only if *all* inputs are 1. Since input B is 0, the output is instantly pulled to **0**. ($Y = 1 \cdot 0 \cdot 1 = 0$).

75.Answer:

They are called Universal Gates because any arbitrary complex digital logic circuit, and all the basic gates (AND, OR, NOT), can be entirely constructed using *only* NAND gates or *only* NOR gates, without requiring any other type of gate.

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